Physical Design
- Planning for floor layout, power distribution, and I/O configuration
- Design Rule Checking (DRC) and Layout Versus Schematic (LVS) testing and verification.
- Performance analysis, including power consumption, signal integrity, and IR drop analysis.
- Estimation of die area for macros/IOs, including calculations based on pad and logic block areas.
- Complete chip design, including packaging and closure.
- Design partitioning and hardening.
- Timing closure sign-off.
- Verification of physical design
- Implementation of low-power design.
- Analysis of static timing (STA).
- Advanced FinFET technologies at deep nodes.
